View IRS2001PBF_730654.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

PRELIMINARY
Data Sheet No. PD60268
IRS2001(S)PbF
HIGH AND LOW SIDE DRIVER
Features
* Floating channel designed for bootstrap operation * Fully operational to +200 V * Tolerant to negative transient voltage, dV/dt immune * Gate drive supply range from 10 V to 20 V * Undervoltage lockout * 3.3 V, 5 V, and 15 V logic input compatible * Matched propagation delay for both channels * Outputs in phase with inputs
Product Summary
VOFFSET IO+/VOUT ton/off (typ.) Delay Matching 200 V max. 130 mA/270 mA 10 V - 20 V 160 ns/150 ns 50 ns
Description
The IRS2001 is a high voltage, high speed power MOSFET and IGBT driver with independent high and low side referenced output channels. Proprietary HVIC and latch immune CMOS technologies enable ruggedized monolithic construction. The logic input is compatible with standard CMOS or LSTTL output, down to 3.3 V logic. The output drivers feature a high pulse current buffer stage designed for minimum driver cross-conduction. The floating channel can be used to drive an N-channel power MOSFET or IGBT in the high side configuration which operates up to 200 V.
Packages
8-Lead SOIC IRS2001S
8-Lead PDIP IRS2001
Typical Connection
up to 200 V VCC
VCC
HIN LIN
VB HO VS LO
TO LOAD
HIN LIN COM
IRS2001
(Refer to Lead Assignments for correct pin configuration). This diagram shows electrical connections only. Please refer to our Application Notes and DesignTips for proper circuit board layout.
www.irf.com
1
IRS2001(S)PbF
PRELIMINARY
Absolute Maximum Ratings
Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute voltages referenced to COM. The thermal resistance and power dissipation ratings are measured under board mounted and still air conditions.
Symbol
VB VS VHO VCC VLO VIN dVS/dt PD RthJA TJ TS TL
Definition
High side floating supply voltage High side floating supply offset voltage High side floating output voltage Low side and logic fixed supply voltage Low side output voltage Logic input voltage (HIN & LIN) Allowable offset supply voltage transient Package power dissipation @ TA +25 C Thermal resistance, junction to ambient Junction temperature Storage temperature Lead temperature (soldering, 10 seconds) (8 lead PDIP) (8 lead SOIC) (8 lead PDIP) (8 lead SOIC)
Min.
-0.3 VB - 25 VS - 0.3 -0.3 -0.3 -0.3 -- -- -- -- -- -- -55 --
Max.
225 VB + 0.3 VB + 0.3 25 VCC + 0.3 VCC + 0.3 50 1.0 0.625 125 200 150 150 300
Units
V
V/ns W C/W
C
Recommended Operating Conditions
The input/output logic timing diagram is shown in Fig. 1. For proper operation the device should be used within the recommended conditions. The VS offset rating is tested with all supplies biased at a 15 V differential.
Symbol
VB VS VHO VCC VLO VIN TA
Definition
High side floating supply absolute voltage High side floating supply offset voltage High side floating output voltage Low side and logic fixed supply voltage Low side output voltage Logic input voltage (HIN & LIN) Ambient temperature
Min.
VS + 10 Note 1 VS 10 0 0 -40
Max.
VS + 20 200 VB 20 VCC VCC 125
Units
V
C
Note 1: Logic operational for VS of -5 V to +200 V. Logic state held for VS of -5 V to -VBS. (Please refer to the Design Tip DT97-3 for more details).
www.irf.com
2
IRS2001(S)PbF
PRELIMINARY
Dynamic Electrical Characteristics
VBIAS (VCC, VBS) = 15 V, CL = 1000 pF and TA = 25 C unless otherwise specified.
Symbol
ton toff tr tf MT
Definition
Turn-on propagation delay Turn-off propagation delay Turn-on rise time Turn-off fall time Delay matching, HS & LS turn-on/off
Min. Typ. Max. Units Test Conditions
-- -- -- -- -- 160 150 70 35 -- 220 220 170 90 50 ns VS = 0 V VS = 200 V
Static Electrical Characteristics
VBIAS (VCC, VBS) = 15 V and TA = 25 C unless otherwise specified. The VIN, VTH, and IIN parameters are referenced to COM. The VO and IO parameters are referenced to COM and are applicable to the respective output leads: HO or LO.
Symbol
VIH VIL VOH VOL ILK IQBS IQCC IIN+ IINVCCUV+ VCCUVIO+
Definition
Logic "1" input voltage Logic "0" input voltage High level output voltage, VBIAS - VO Low level output voltage, VO Offset supply leakage current Quiescent VBS supply current Quiescent VCC supply current Logic "1" input bias current Logic "0" input bias current VCC supply undervoltage positive going threshold VCC supply undervoltage negative going threshold Output high short circuit pulsed current
Min. Typ. Max. Units Test Conditions
2.5 -- -- -- -- -- -- -- -- 8 7.4 130 -- -- 0.05 0.02 -- 30 150 3 -- 8.9 8.2 290 -- 0.8 0.2 0.1 50 55 270 10 1 9.8 9 -- mA V VO = 0 V VIN = Logic "1" PW 10 s VO = 15 V VIN = Logic "0" PW 10 s A VIN = 0 V or 5 V VIN = 5 V VIN = 0 V VB = VS = 200 V V IO = 2 mA VCC = 10 V to 20 V
IO-
Output low short circuit pulsed current
270
600
--
www.irf.com
3
IRS2001(S)PbF
PRELIMINARY
Functional Block Diagram
VB Q PULSE FILTER R S VS HO
HV LEVEL SHIFT
HIN
PULSE GEN UV DETECT
VCC
LIN
LO
COM
IRS2001
www.irf.com
4
IRS2001(S)PbF
PRELIMINARY
Lead Definitions
Symbol
HIN LIN VB HO VS VCC LO COM
Description
Logic input for high side gate driver output (HO), in phase Logic input for low side gate driver output (LO), in phase High side floating supply High side gate drive output High side floating supply return Low side and logic fixed supply Low side gate drive output Low side return
Lead Assignments
8 Lead PDIP
8 Lead SOIC
IRS2001PBF Part Number
IRS2001SPbF
www.irf.com
5
IRS2001(S)PbF
PRELIMINARY
HIN LIN
HIN LIN
ton
50%
50%
tr 90%
toff 90%
tf
HO LO
Figure 1. Input/Output Timing Diagram
HO LO
10%
10%
Figure 2. Switching Time Waveform Definitions
HIN LIN
50%
50%
LO
HO
10%
MT 90%
MT
LO
HO
Figure 3. Delay Matching Waveform Definitions
www.irf.com
6
IRS2001(S)PbF
PRELIMINARY
500 Turn-On Delay Time (ns) 400 300 200 100 Max. Turn-On Delay Time (ns)
500 400 300 200
Max.
Typ.
100 0
Typ.
0 -50
-25
0
25
50
75
100
125
10
12
14
16
18
20
Temperature (C)
VBIAS Supply Voltage (V)
Figure 6A. Turn-On Time vs. Temperature
Figure 6B. Turn-On Time vs. Supply Voltage
500
Turn-On Delay Time (ns)
5 00
400 300 200 100 0 0 2 4 6 8 10 12 14 16 18 20
Turn-Off Delay Time (ns)
4 00 3 00 2 00 1 00 T yp . 0 -50 -25 0 25 50 75 1 00 1 25 M ax .
Input Voltage (V)
Temperature (C)
Figure 6C. Turn-On Time vs. Input Voltage
Figure 7A. Turn-Off Time vs. Temperature
500
500
Turn-Off Delay Time (ns)
Turn-Off Delay Time (ns)
400 300 200 Typ. 100 0 10 12 14 16 18 20 Max.
400 300 200 100 0 0 2 4 6 8 10 12 14 16 18 20 Typ. Max.
VBIAS Supply Voltage (V)
Input Voltage (V)
Figure 7B. Turn-Off Time vs. Supply Voltage www.irf.com
Figure 7C. Turn-Off Time vs. Input Voltage 7
IRS2001(S)PbF
PRELIMINARY
500
Turn-On Rise Time (ns) Turn-On Rise Time (ns)
500 400 300
Max.
400 300 200 100
Typ.
200 100
Typ.
Max.
0 -50 -25 0 25 50 75 100 125
Temperature (C)
0 10 12 14 16 18 20
VBIAS Supply Voltage (V)
Figure 9A. Turn-On Rise Time vs. Temperature
Figure 9B. Turn-On Rise Time vs. Voltage
200
Turn-Off Fall Time (ns) Turn-Off Fall Time (ns)
200 150 100 50
Typ.
150 100
Max.
Max.
50
Typ.
0 -50 -25 0 25 50 75 100 125
Temperature (C)
0 10 12 14 16 18 20
VBIAS Supply Voltage (V)
Figure 10A. Turn-Off Fall Time vs. Temperature
8 7 Input Voltage (V) 6 5 4 3 2 1 0 -50 -25 0 25 50
o
Min.
Figure 10B. Turn-Off Fall Time vs. Voltage
8 7 Input Voltage (V) 6 5 4 3 2 1 0
Min.
75
100
125
10
12
14
16
18
20
Temperature ( C)
VBIAS Supply Voltage (V)
Figure 12A. Logic "1" Input Voltage vs. Temperature www.irf.com
Figure 12B. Logic "1" Input Voltage vs. Voltage 8
IRS2001(S)PbF
PRELIMINARY
4 3 .2
4 3.2
Input t V o l g e (V ) I p u Voltage (V) n ta
2 .4 1 .6 M ax. 0 .8 0 -50 -25 0 25 50 75 1 00 1 25
Temperature (C)
Input Voltage (V ) I nput V o l e (V) tag
2.4 1.6 M ax . 0.8 0 10 12 14 16 18 20
Vcc Supply Voltage (V)
Figure 13A. Logic "0" Input Voltage vs. Temperature
High Level Output Voltage (V) High Level Output Voltage (V)
0.5 0.4 0.3 0.2 0.1
Typ.
Figure 13B. Logic "0" Input Voltage vs. Supply Voltage
0.5 0.4 0.3 0.2 0.1
Typ.
Max.
Max.
0.0 -50 -25 0 25 50
o C)
0.0 10 12 14 16 18 20 V BIAS Supply V oltage (V )
Vcc Supply Voltage (V)
75
100
125
Temperature (
Figure 14A. High Level Output Voltage vs. Temperature
Low Level Output Voltage (V)
Low Level Output Voltage (V) 0.5 0.4 0.3 0.2 0.1 0.0 -50 -25 0 25 50 ( oC) 75 100 125 Temperature
Max.
Figure 14B. High Level Output vs. Supply Voltage
0.5 0.4 0.3 0.2
Max.
0.1
Typ.
Typ.
0 10 12 14 16 18 20 V BIAS Supply Voltage (V)
Figure 15A. Low Level Output Voltage vs. Temperature www.irf.com
Figure 15B. Low level Output vs.Supply Voltage 9
IRS2001(S)PbF
PRELIMINARY
Offset Supply Leakage Current (A) (A) Offset Supply Leakage Current (A ) (A)
500 400 300 200 100 0 -50 -25 0 25 50 75 100 125
500 400 300 200 100 0 0 100 200 300 400 500 600
M ax.
Max.
Temperature (C)
VB Boost Voltage (V)
Figure 16A. Offset Supply Current vs. Temperature
1 50
150
Figure 16B. Offset Supply Current vs. Voltage
VBS Supply Current (A)
1 20 90 60 M ax . 30 T yp . 0 -50 -25 0 25 50 75 1 00 1 25
VBS Supply Current (A)
120 90 60 30 Ty p. 0 10 12 14 16 18 20
Max .
Temperature (C)
VBS Floating Supply Voltage (V)
Figure 17A. VBS Supply Current vs. Temperature
700 700
Figure 17B. VBS Supply Current vs. Voltage
Vcc Supply Current (A)
600 500 400 300 200 100 0 -5 0 -2 5 0 25 50 75 100 125 Typ. M ax.
Vcc Supply Current (A)
600 500 400 300 200 100 Typ. 0 10 12 14 16 18 20 M ax.
Temperature (C)
Vcc Supply Voltage (V)
Figure 18A. Vcc Supply Current vs. Temperature www.irf.com
Figure 18B. Vcc Supply Current vs. Voltage 10
IRS2001(S)PbF
PRELIMINARY
30
30
Logic 1" Input Current (A)
Logic 1" Input Current (A)
25 20 15 10 M ax. 5 Typ. 0 -5 0 -2 5 0 25 50 75 100 125
25 20 15 10 5 0 10 12 14 16 18 20 M ax. Typ.
Temperature (C)
Vcc Supply Voltage (V)
Figure 19A. Logic"1" Input Current vs. Temperature
5
Logic "0" Input Current (A) Logic "0" Input Current (A)
Figure 19B. Logic"1" Input Current vs. Voltage
5 4 3 2 Max. 1 0 10 12 14 16 Vcc Supply Voltage (V) 18 20
4 3 2 Max. 1 0 -50
-25
0
25 50 75 Temperature (C)
100
125
Figure 20A. Logic "0" Input Current vs. Temperature
11 10 9 8 7 6 -50 -25 0 25 50 75 100 125
Temperature (C)
VCC UVLO Threshold - (V) VCC UVLO Threshold +(V)
Figure 20B. Logic "0" Input Current vs. Voltage
11
M ax. Typ. Mi n.
10 Max. 9 Typ. 8 7 Min.
6 -50
-25
0
25
50
75
100
125
Temperature (C)
Figure 21A. Vcc Undervoltage Threshold(+) vs. Temperature www.irf.com
Figure 21B. Vcc Undervoltage Threshold(-) vs. Temperature 11
IRS2001(S)PbF
PRELIMINARY
500 400
Typ.
500
Output Source Current (mA) ) (
Output Source Current (mA)
400 300 200
Typ.
300 200 100 0 -50 -25 0 25 50
o
Min.
100
Min.
0
75 100 125
10
12
14
16
18
20
Temperature ( C)
Temperature (C)
VBIAS Supply Voltage (V)
Figure 22A. Output Source Current vs. Temperature
1000
Output Sink Current (mA) Output Sink Current (mA)
Figure 22B. Output Source Current vs. Supply Voltage
1000 800 600 400
Typ.
800
Typ.
600 400
Min.
200 0 -50
200
Min.
0 -25 0 25 50 75 100 125 10 12 14 16 18 20 C) Temperature (C)
VBIAS Supply Voltage (V)
Figure 23A. Output Sink Current vs. Temperature
Figure 23B. Output Sink Current vs. Supply Voltage
www.irf.com
12
IRS2001(S)PbF
PRELIMINARY
Case Outlines
8 Lead PDIP
D A 5 B
FOOTPRINT 8X 0.72 [.028]
01-6014 01-3003 01 (MS-001AB)
INCHES MIN .0532 .013 .0075 .189 .1497 MAX .0688 .0098 .020 .0098 .1968 .1574 MILLIMETERS MIN 1.35 0.10 0.33 0.19 4.80 3.80 MAX 1.75 0.25 0.51 0.25 5.00 4.00
DIM A b c D
A1 .0040
6 E
8
7
6
5 H 0.25 [.010] A
E
6.46 [.255]
1
2
3
4
e e1 H K L
8X 1.78 [.070]
.050 BASIC .025 BASIC .2284 .0099 .016 0 .2440 .0196 .050 8
1.27 BASIC 0.635 BASIC 5.80 0.25 0.40 0 6.20 0.50 1.27 8
6X
e e1
3X 1.27 [.050]
y
A C 0.10 [.004] y
K x 45
8X b 0.25 [.010]
NOTES:
A1 CAB
8X L 7
8X c
1. DIMENSIONING & TOLERANCING PER ASME Y14.5M-1994. 2. CONTROLLING DIMENSION: MILLIMETER 3. DIMENSIONS ARE SHOWN IN MILLIMETERS [INCHES]. 4. OUTLINE C ONFORMS TO JEDEC OUTLINE MS-012AA.
5 DIMENSION DOES NOT INCLUDE MOLD PROTRUSIONS. MOLD PROTRUSIONS NOT TO EXCEED 0.15 [.006]. 6 DIMENSION DOES NOT INCLUDE MOLD PROTRUSIONS. MOLD PROTRUSIONS NOT TO EXCEED 0.25 [.010]. 7 DIMENSION IS THE LENGTH OF LEAD FOR SOLDERING TO A SUBSTRATE.
8 Lead SOIC
www.irf.com
01-6027 01-0021 11 (MS-012AA)
13
IRS2001(S)PbF
PRELIMINARY
Tape & Reel 8-lead SOIC
LOAD ED TA PE FEED DIRECTION
B
A
H
D F C
N OT E : CO NTROLLING D IM ENSION IN MM
E G
C A R R I E R T A P E D IM E N S I O N F O R 8 S O I C N M etr ic Im p er i al Co d e M in M ax M in M ax A 7 .9 0 8.1 0 0. 31 1 0 .3 18 B 3 .9 0 4.1 0 0. 15 3 0 .1 61 C 11 .7 0 1 2. 30 0 .4 6 0 .4 84 D 5 .4 5 5.5 5 0. 21 4 0 .2 18 E 6 .3 0 6.5 0 0. 24 8 0 .2 55 F 5 .1 0 5.3 0 0. 20 0 0 .2 08 G 1 .5 0 n/ a 0. 05 9 n/ a H 1 .5 0 1.6 0 0. 05 9 0 .0 62
F
D C E B A
G
H
R E E L D IM E N S I O N S F O R 8 S O IC N M etr ic Im p er i al Co d e M in M ax M in M ax A 32 9. 60 3 30 .2 5 1 2 .9 76 13 .0 0 1 B 20 .9 5 2 1. 45 0. 82 4 0 .8 44 C 12 .8 0 1 3. 20 0. 50 3 0 .5 19 D 1 .9 5 2.4 5 0. 76 7 0 .0 96 E 98 .0 0 1 02 .0 0 3. 85 8 4 .0 15 F n /a 1 8. 40 n /a 0 .7 24 G 14 .5 0 1 7. 10 0. 57 0 0 .6 73 H 12 .4 0 1 4. 40 0. 48 8 0 .5 66
www.irf.com
14
IRS2001(S)PbF
PRELIMINARY
LEADFREE PART MARKING INFORMATION
Part number
IRSxxxxx YWW? ?XXXX
Lot Code (Prod mode - 4 digit SPN code) IR logo
Date code
Pin 1 Identifier ? P MARKING CODE Lead Free Released Non-Lead Free Released
Assembly site code Per SCOP 200-002
ORDER INFORMATION
8-Lead PDIP IRS2001PBF 8-Lead SOIC IRS2001SPbF 8-Lead SOIC Tape & Reel IRS2001STRPbF
The SOIC-8 is MSL2 qualified. This product has been designed and qualified for the industrial level. Qualification standards can be found at www.irf.com IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245 Tel: (310) 252-7105 Data and specifications subject to change without notice. 6/28/2006
www.irf.com
15

▲Up To Search▲

Price & Availability of IRS2001PBF

	To Download IRS2001PBF Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .